1. Field of the Invention
The present invention relates to a technology to reduce power consumption in a data processing apparatus which mainly operates in a manner of pipeline processing.
2. Description of the Related Art
Demand for improvement in processing speed is increasing every year in a data processing apparatus that performs picture processing and audio processing.
A pipeline processor which a plurality of calculating units are connected in series to perform parallel processing realizes the improvement in processing speed.
Document 1 (published Japanese Patent Application Laid-Open No. HEI10-334225) discloses a data processing apparatus comprising a plurality of calculating units connected in series and a plurality of memories which connect each of the calculating units. Each memory consists of a double buffer.
FIG. 17 is a block diagram illustrating the data processing apparatus disclosed in Document 1.
A data processing apparatus 200 has four calculating units 201 to 204 and three memories 205 to 207 which connect these four calculating units. The calculating units 201 to 204 are connected in series, and perform predetermined calculation for the inputted data therein. Each of the memories 205 to 207 is structured by a double buffer, and stores data outputted from a calculating unit at the previous stage thereof and, at the same time, outputs data previously stored therein to a calculating unit at the following stage thereof.
For example, the memory 205 stores output data of the calculating unit 201 and outputs the previously stored data to the calculating unit 202.
The data inputted into the calculating unit 201 is first calculated by the calculating unit 201, and the calculating unit 202 at the following stage receives a calculation result. The calculating unit 202 performs calculation based on the received calculation result, and passes a calculation result to the calculating unit 203 at the following stage via the memory 206. The calculating unit 201 performs calculation to the subsequent input data while the calculating unit 202 performs the predetermined calculation. That is, the calculating units 201 to 204 operate in parallel.
As described above, pipeline processing is realized by series connection of the calculating units 201 to 204 via the memories 205 to 207 therebetween.
However, even when dealing with an application which does not need high processing capability, the data processing apparatus in the prior art performs pipeline processing, activating all the calculating units in the same period. Therefore, the data processing apparatus in the prior art performs pipeline calculation corresponding to the maximum required capability thereof.
For this reason, a problem arises that unnecessary power is often consumed, in excess of the requirement of the application. The problem results in insufficient reduction of power consumption, specifically unfavorable increase of a peak power.
On the other hand, in picture processing and audio processing, even when the picture processing and audio processing are performed according to the same standard, required processing capability differs in many cases, depending on the required picture size or audio quality (for example, a CIF picture and a QCIF picture).
Therefore, there arises another problem that calculation processing responding to changes of the required processing capability can not be practiced during processing of the same application. This problem results in wasteful power consumption.